Micrel, Inc.
MIC2310
July 2008
21
M9999-070108-A
HW_FLT Asserted by MOSFET DS Short after
Steady-state Operation then ENABLE = HIGH-to-
LOW
Figure 9 illustrates the behavior of the controller to a
shorted DS MOSFET condition after steady-state
operation is achieved via a nominal start-up. Note that
the load capacitor at start-up was charged in a
controlled dI
D
/dt mode and assertion of the controllers
PWRGD digital output occurs when the output load
voltage profile is higher than the controllers V
PGH
threshold voltage and the V
GS
of the external
MOSFET is higher than the controllers V
GSPGH
threshold voltage. Upon the application of a HIGH-to-
LOW transition on ENABLE by the service processor,
the GATE drive circuit is disabled, the weak GATE
current sink is enabled, the DISCH output goes high,
and the t
DS-SSFAULT
timer is started. With the ENABLE
input LOW, a voltage monitor circuit for the controllers
SOURCE pin (i.e., V
OUT
) is enabled. If there is a DS
short, the voltage at the source will not drop to 0V
even though the GATE is OFF. If the output voltage at
the SOURCE pin remains higher than the controllers
V
SRCFT(EXT)
threshold voltage when the t
DS-SSFAULT
timer
terminates, the HW_FLT digital output is asserted. To
repair the damaged MOSFET and to reset the
HW_FLT digital output and the controller, the service
processor instructs the main supply to turn off the V
CC
supply voltage to the controller such that V
REG
falls
below the controllers V
VREG(UVLOL)
threshold voltage.
Figure 9. Hardware Fault by a MOSFET DS Short after Steady-State Operation
(ENABLE = HIGH-to-LOW)
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